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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
WRITE TO OUTPUT PORTS REGISTERS
(P4)
SCL
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
COMMAND BYTE
SDA
S
1
0
0
1
1
A1
A0
0
A
0
0
0
0
0
1
0
0
A
MSB
DATA
LSB
A A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP
ACKNOWLEDGE
P9 TO P1
Figure 16. Write to Output Port Registers
READ FROM INPUT PORTS REGISTERS
t PPV
DATA VALID
SCL
1
2
3
4
5
6
7
8
9
SDA
S
1
0
0
1
1
A1
A0
1
A
MSB
DATA1
LSB
A
MSB
DATA4
LSB
NA
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTE R
STOP
NO ACKNOWLEDGE
P9 TO P1
DATA1
DATA2
DATA3
DATA4
Figure 17. Read from Input Port Registers
INTERRUPT VALID/RESET
t PH
t PSU
SCL
1
2
3
4
5
6
7
8
9
SDA
S
1
0
0
1
1
A1
A0
1
A
MSB
DATA2
LSB
A
MSB
DATA3
LSB
NA
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
STOP
NO ACKNOWLEDGE
P9 TO P1
DATA1
DATA2
DATA3
INT
t IV
t IR
t IV
t IR
Figure 18. Interrupt and Reset Timing
Operation with Multiple Masters
If the MAX7302 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7302
should use a repeated start between the write that sets
the MAX7302’s address pointer, and the read(s) that
takes the data from the location(s). This is because it is
possible for master 2 to take over the bus after master
1 has set up the MAX7302 ’s address pointer, but
before master 1 has read the data. If master 2 subse-
quently changes the MAX7302’s address pointer, then
master 1’s delayed read can be from an unexpected
location.
Bus Timeout
Clear device configuration register 0x27 bit D7 to
enable the bus timeout function (see Table 4), or set it
to disable the bus timeout function. Enabling the time-
out feature resets the MAX7302 serial-bus interface
when SCL stops either high or low during a read or
write. If either SCL or SDA is low for more than nominal-
ly 31ms after the start of a valid serial transfer, the inter-
face resets itself and sets up SDA as an input. The
MAX7302 then waits for another START condition.
24
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